High-speed printing system



SePL 2, 1958 E. c. NELSON 2,850,566

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AGENT.

United States Patent Otlice 2,850,566 Patented Sept. 2, 1958 HIGH-SPEED PRINTING SYSTEM Eldred C. Nelson, Los Angeles, Calif., assigner, by mesne assignments, to Hughes Aircraft Company, a corporation of Delaware Application September 8, 1953, Serial No. 379,045

14 Claims. (Cl. 178-23) This invention relates to a high-speed printing system, and more particularly to a serially operable high-speed printing system in which the information characters in a line of intelligence information to be printed are sequentially compared with each type character which is sequentially presented to be printed.

Relatively recent advances in the field of high-speed electronic data-processing machines have fostered the need for reliable high-speed output devices to convert processed intelligence information in the form of electrical signals to visual indications of the results of the dataprocessing operation. In particular, there has been an ever increasing need in the art for high-speed printing systems to rapidly convert the electrical output signals from the data-processing machine to a printed record.

The high-speed printing systems of the prior art have one basic mode of operation, namely parallel, wherein all like characters in the line of intelligence information are printed simultaneously, the printing being accomplished by selectively energizing a plurality of printing transducers to bring an intermittently movable printing medium into engagement with a rotatable straight-line printing cylinder having a plurality of longitudinally aligned rows of type characters disposed about its periphery. The number of printing transducers employed is dependent upon the number of line spaces or columns in the line of intelligence information to be printed, one transducer being provided for each column on the printing medium.

In these high-speed printing systems of the prior art, each printing transducer is coupled to an associated electronic register, usually a tlip-llop counter, the number of counters corresponding to the number of printing transducers incorporated in the system. In operation the signals corresponding to the information characters in the line of intelligence information to be printed are rst entered, either serially or in parallel, into the counters corresponding to the spacing of the information characters in the line of intelligence information. The counters are then pulsed in parallel by an electrical pulse signal generated by the associated printing cylinder as it rotates, the count in each counter changing one number for each pulse received, one pulse being received each time the printing cylinder has rotated suiliciently to place the succeeding row of type characters in printing position.

As cach counter becomes full or empty, depending upon whether a count-up or count-down counting sequence is employed, the counter generates an electrical output signal for energizing its associated printing transducer to print on the printing medium the type character in printing position on the printing cylinder. Thus, if several counters have the same information signals entered therein prior to the pulsing operation, the counters Will generate output signals simultaneously for energizing their associated printing transducers simultaneously to print the same information character in their respectively associated columns or spaces on the printing medium.

One of the principal disadvantages of these prior art printing systems is that they require tremendous multiplication of electrical circuitry and components, such as vacuum tubes, and are therefore almost prohibitively expensive. Other logical consequences of their inherent complexity are unreliability of the system as a whole and excessive size and weight. Another significant disadvantage of these prior art systems is that they are incapable of printing at speeds in excess of live to ten lines per second, even when the intelligence information is restricted to numerical information alone.

The present invention, on the other hand, obviates the above and other disadvantages of the prior art printing systems by providing a reliable and relatively inexpensive serially operable high-speed printing system for printing the information characters in a line of intelligence information by sequentially comparing each information character with each type character which is sequentially presented to be printed. According to the fundamental concept of this invention, a plurality of serially applied electrical information signals corresponding respectively to the information characters in the line of intelligence information are sequentially compared with an electrical character signal corresponding to the type character in printing position on an associated printing cylinder to selectively actuate a plurality of associated printing transducers to print on a printing medium the type characters corresponding to the information characters.

More particularly, according to the preferred embodiment of the present invention, the electrical information signals correspond respectively to the binary-coded numerical equivalents of the information characters and are serially applied to a single electronic comparator network where they are compared with an electrical character signal which is binary coded in accordance with the rotation of the printing cylinder. The comparator network functions to produce a comparator output signal each time an information character in the line of intelligence information corresponds to the type character in printing position. Each comparator output signal is applied in turn to a distributor network which is connected to the printing transducers and which is responsive to the application of a comparator output signal for selectively energizing the printing transducers. The transducer energized corresponds to the spacing in the line of intelligence information of the information character being compared in the comparator network, thereby printing in the corresponding space on the printing medium the type character corresponding to the information character being compared.

Each line of intelligence information is compared sequentially with the type characters which may be printed by continuously recirculating the electrical information signals and by applying these signals to the comparator network once for each different electrical character signal. Accordingly, one comparator output signal is produced for each information character, thereby selectively energizing the printing transducers to print the type characters corresponding to all of the information characters in the line of intelligence information.

The printing system of the present invention may include either the conventional straight-line printing cylinder, or a continuously rotatable skeyed-type printing cylinder similar to those disclosed in copending U. S. patent application, Serial No. 360,998, for Printing Cylinders for High-Speed Printing Systems, `by R. A. Hartley, filed June 11, 1953. In addition, by employing an interference type printing transducer similar to that disclosed in copending U. S. patent application, Serial No. 377,818, for High-Speed Electromechanical Printing Transducer," by S. M. Fomenko et al., tiled October l, 1953, identical information characters in the line of intelligence informa- 3 tion may be printed either in sequence, with a skewedltype cylinder, or simultaneously with a straight-line cylin- Another basic feature of the high-speed printing system of this invention is the use of logical network theory to provide simplified electronic circuits which further increase the inherent reliability and speed of the system and which further decrease both the initial and operating expense of the system. In practice it has been found that the printing system of the present invention is capable of printing intelligence information, represented hy as many as sixty different type characters, at speeds in excess of fifteen lines per second.

It is, therefore, an object of this invention to provide a reliable and relatively inexpensive serially operable high-speed printing system capable of printing intelligence information, at speeds in excess of fifteen lines per second.

Another object of this invention is to provide a logically designed high-speed printing system for printing the information characters in a line of intelligence information as corresponding type characters on a printing medium by sequentially comparing the information characters with each type character which may be printed.

It is also an objecct of this invention to provide a highspeed printing system for printing a line of intelligence information by sequentially comparing the information characters in the line of intelligence information with each type character which may be printed to selectively energize a plurality of associated printing transducers to print in corresponding column spaces on a printing medium the type characters corresponding to each of the information characters.

An additional object of this invention is to provide a high-speed printing system for printing the information characters in a line of intelligence information, stored in the form of coded binary numbers, by sequentially comparing electrical information signals, corresponding to the binary numbers, with electrical signals corresponding to the type character in printing position to produce electrical output signals for selectively energizing a plurality of printing transducers, corresponding to the column spacing of the information characters.

Stiil another object of this invention is to provide a high-speed printing system in which electrical signals corresponding to the sequential information characters in a line of binary-coded intelligence information are sequentially compared with electrical signals corresponding to the type character in printing position for energizing a printing transducer, corresponding to the column spacing of the information character being compared, each time the information character being compared corresponds to the type character in printing position.

It is another object of this invention to provide a highspeed printing system for printing a line of binary-coded intelligence information by sequentially comparing all of the information characters in the line of intelligence information with electrical signals corresponding to each of the type characters which may be printed for selectively energizing a plurality of printing transducers, corresponding in number to the number of information characters in the line of intelligence information, to print on a printing medium the type characters c-orresponding to the information characters in the line of intelligence.

It is still another object of this invention to provide a high-speed printing system for printing intelligence information, serially presented as electrical information signals corresponding to a plurality of binary-coded information characters, by sequentially comparing the information signals with electrical signals corresponding to the sequential type characters which are in printing position to produce an electrical comparison signal each time an information character corresponds to the type character in printing position, and by selectively energizing a printing transducer corresponding to the column spacing of the information character being compared in response to each comparison signal.

The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings, in which a preferred embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the limits of invention.

Fig. 1 is a block diagram of a high-speed printing systern, according to the present invention;

Fig. 2 is a schematic diagram of one form of character counter which may be utilized in the printing system of Fig. 1;

Fig. 3 is a schematic diagram of a serially operable comparator network which may be employed with the character counter shown in Fig. 2 in the high-speed printing system of Fig. 1;

Figs. 4 and 5 are schematic diagrams of a column counter and a transducer energizing network, respectively, which may be employed in combination in the highspeed printing system of Fig. l for controlling the energization of the printing transducers;

Fig. 6 is a schematic diagram, partly in block diagram form, of one type of order control network which may be utilized to control the operational functions of the high-speed printing system of Fig. l;

Fig. 7 is a schematic diagram of a modified character counter which may be employed with the serial comparator of Fig. 3 in the high-speed printing system of this invention;

Figs. 8 and 9 are schematic diagrams of a modified column counter and a transducer energizing network, respectively, which may be employed in the high-speed printing system of this invention;

Fig. 10 is a schematic diagram of a different type of character counter which may be utilized in the high-speed printing system of Fig. l;

Fig. ll is a schematic diagram of a parallel comparator circuit which may be utilized in cooperation with the character counter shown in Fig. 10 in the high-speed printing system of Fig. l;

Fig. 12 is a circuit diagram illustrating a typical and" gate employing diode rectifiers;

Fig. 13 is a circuit diagram illustrating a typical or gate;

Fig. 14 is a perspective view schematically illustrating a printing cylinder mechanism; and

Fig. l5 is a sectional view illustrating a type of printing transducer.

Referring now to the drawings, there is shown in Fig. 1 a serially operable high-speed printing system, according to the present invention, for printing on a printing medium intelligence information stored in the form of binary-coded electrical signals in a data storage unit 102, The high-speed printing system includes four basic cornponents, namely, data storage unit 102 for storing the intelligence information to be printed, a high-speed printer 104 for printing on medium 100 the type characters corresponding to the information characters in the stored intelligence information, a logical control network 106 for synchronizing the operation of data storage 102 with printer 104 to control the printing sequence of the individual characters of the stored intelligence information, and a distributor network 108 for selectively controlling the operation of printer 104 so that each information character is printed in the proper space on printing medium 100.

In order to simplify the description of the high-speed printing system of this invention, it will first be assumed that one full line of intelligence information to be printed is stored in data storage unit 102. It will also be assumed for purposes of illustration that each line of intelligence information includes a predetermined number of information characters corresponding to the number of characters which may be printed on one line of printing medium 100, each information character being represented by a sixdigit electrical signal weighted in the 32-16-8-4-2-1 binary code. The time interval required to serially present each binary digit signal of each information character at the output circuit of the data storage unit will hereinafter be termed a digit time interval. while the time required to serially present the six-digit signal corresponding to an information character will be termed a word time interval. Similarly, the time required to serially present the full line of stored intelligence information at the output circuit of the data storage unit will hercinafter be termed a line time interval, while the time rcquired to print the full line of intelligence information will be termed a line printing interval.

Data storage unit 102 preferably includes a magnetic memory unit, such as a rotatable magnetic drum 110, an associated clock pulse generator 112, and associated electronic circuits. Magnetic drum 110 is mechanically coupled to and rotated by a drive source 111 in printer 104, and includes at least three magnetic tracks 114, 116, and 118 respectively, for storing binary-coded intelligence information and order signals in the form of magnetized cells on the drum periphery.

The associated electrical circuits of data storage unit 102 include three reading circuits 120, 122, and 124 which are positioned adjacent magnetic tracks 114, 116, and 118, respectively, and are responsive to the magnetization of their associated tracks for producing electrical signals corresponding to the binary values represented by the magnetization of the tracks. The electrical signals produced by reading circuits 120, 122, 124 are applied, in turn, to three respectively associated ilip-op or bistable multivibrator circuits FI, FW, and F0 to set these iiipops to conduction states corresponding to the binary values represented by the applied signals. Thus, if the magnetization of a particular cell on a magnetic track corresponds to the binary value one, the associated ipop is set to the conduction state corresponding to the binary value one, whereas the Hip-flop is set to the other conduction state if the magnetization of the cell on the associated magnet track corresponds to the binary value zero.

It will be assumed that one complete line of binarycoded intelligence information is serially entered on magnetic track 114 through an associated writing circuit, not shown, so that the complete line of intelligence information may be serially read by reading circuit 120 once during each line time interval, thereby serially presenting at the output circuit of flip-Hop FI electrical voltagestate signals corresponding to the sequential binary digits of each of the successive information characters in the stored line of intelligence information. It will also be assumed for purposes of illustration that the intelligence information is serially presented at the output circuit of flip-flop FI in the order of least significant binary digit first.

Magnetic track 116 and its associated reading circuit are utilized to set iiip-op FW to the conduction state corresponding to the binary value one during the sixth or last digit time interval of each word time interval. Flipop FO, on the other hand, is set to the conduction state corresponding to the binary value one during the sixth or last digit time interval of the last word time interval of each line time interval. In other words, flip-hop FO is set to the conduction state corresponding to the binary value one during the last digit time interval of each circulation of the intelligence information by the magnetic drum.

Clock pulse generator 112 is utilized to produce a peri- Odically recurring electrical clock pulse of predetermined polarity, one clock pulse occurring during each digit time interval. It will hereinafter be assumed that each clock pulse is relatively sharp negative electrical pulse which occurs at the beginning of each digit time interval.

High-speed printer 104 includes three basic elements, namely, drive mechanism 111, a rotatable printing cylinder 132 coupled to the drive mechanism, and a transducer network including a plurality of selectively energizable printing transducers -1, 130-2, 130-3, 130-(11-2), 130-(n-1), and 13G-(n, respectively, positicned adjacent printing cylinder 132 and adapted to cooperate with the printing cylinder for printing intelligence information on printing medium 100.

The printing transducers are operable under the control of distributor network 108 and are preferably of the type disclosed in copending U. S. patent application, Serial No. 377.956, for Electromechanical Transducers, by E. M. Baldwin et al., filed October l, 1953. These transducers are preferred because of their relatively high efficiency and their exceptionally high operating speeds. It will be recognized however, that other printing transducers may be utilized with the high-speed printing system of this invention.

Printing cylinder 132 may be a skewed-type printing cylinder similar to those disclosed in the aforementioned copending application by Richard A. Hartley, or may be of the conventional straight-line type in which a plurality of rows of type characters are longitudinally disposed about the periphery of the printing cylinder. In each of these two basic forms of printing cylinders, one row of type characters is provided for each different type character which may be printed, each row including a plurality of identical type characters corresponding in number to the number of printing transducers employed in the printer.

A typical example of such a cylinder is illustrated in Fig. 14. In an effort to simplify this illustration, the type characters on the face of the cylinder are represented only as numerals. These type characters are generally designated and range from 0 through 9, circumferentially, The type of printing cylinder herein illustrated involves skewed rows of type characters in which each row represents a different type character and the characters in individual rows are identical. The rows are skewed in an amount wherein the character at one end of one row occupies a position in a plane axially of the cylinder, approximately overlapping the number at the other end of an adjacent row.

The minimum number of characters in each row usually corresponds to the number of different characters circumferential of the cylinder. The characters are spaced in the rows as required to provide proper type spacing for printing purposes. A printing transducer is associated with each circumferential ring of characters. These transducers are arranged in spaced relation axially of the cylinder in correspondence with the axial spacing of the characters on the printing cylinder. The printing transducers lie in an axial plane which substantially parallels the axis of rotation of the printing cylinder and are preferably radially disposed of the printing cylinder.

Assuming clockwise rotation of the printing cylinder as viewed. the first character of a skewed row which appears beneath a printing transducer is on the left side of the printing cylinder. Continued rotation of the cylinder thus sequentially brings the characters, from left to right of a row, beneath the respective printing transducers. Thus, by controlling the printing transducers in time sequence with the appearance of the characters in a skewed row beneath the respective transducers and further controlling the transducers each time a character in the line of intelligence information to be printed, corresponds to the characters of the type row in printing position, a complete line of characters may be printed across a printing medium such as a web or a sheet of paper passing over the printing cylinder beneath the transducers.

In keeping with the numbering in Fig. 1 of the drawings the transducers are identified as 130-1 through 13G-n. It is to be appreciated, however, that in the interest of drawing convenience, a printing cylinder bearing only numeral-type characters has been illustrated in Fig. 14, having a definite length sutlicient only to contain the required number of type numbers in the respective skewed rows. Thus, the cylinder is not illustrated with an intermediate break as in Fig. 1. In Fig. 14. the driving means is schematically represented as 111 and the connection of the drive mechanism 111 to the roll of printing material has not been shown. Such details are within the skill of the ordinary mechanic.

A type of printing transducer which might be employed with the arrangement herein illustrated appears in Fig. and is identified 130-1. Since the printing transducers are identical, this illustration, of course, is typical of all of the transducers. Reference is made hereinabove to a patent application of E. N. Baldwin et al. for Electromechanical Transducer." The transducer therein illustrated differs in principle from that illustrated in Fig. 15 depending primarily upon the kinetic energy stored in a rotating body for supplying mechanical energy for operating the printing hammer. The representation in Fig. 15 in this application is purely of a schematic nature to indicate an operable arrangement for actuating the type hammer and is not to be construed as representing a preferred way or the only way of actuating the type hammer.

In Fig. 15 type hammer 161 is driven by a solenoid plunger 162 which is spring loaded by a spring 163 to the retracted position illustrated. The solenoid plunger 162 is slidably mounted in a housing 164 of magnetic material and the plunger mass is axially eccentric with respect to the magnetic field produced by an annular coil 165 disposed within the magnetic housing and through which the solenoid plunger strokes. It will be appreciated that energization of coil 165 produces a magnetic field linking the solenoid plunger 162 and the plunger moves in a direction tending to center its mass in the magnetic field. The direction of motion being downwardly, as viewed, compressing spring 163 and displacing type hammer 161 downwardly. For the position of the printing transducers illustrated in Fig. 14 this downward displacement of the type hammer impinges printing sheet 100 against the characters on the printing cylinder transferring the character impression by means of a carbon tape, not shown, or other suitable printing transfer medium, on to the underside of the printing sheet 100. The manner in which the selective and synchronous control of the transducers is achieved for printing a line of intelligence information is described hereinafter. Further details as to a practical type of printing transducer and further details with respect to the printing cylinder per se may be had by reference to the aforesaid copending applications of E. M. Baldwin et al. and Richard A. Hartley, respectively.

Printing cylinder 132 is preferably continuously rotated by drive mechanism 111, although intermittent rotation of the type cylinder is permissible with the conventional printing cylinders of the prior art. The speed of rotation of the printing cylinder relative to that of magnetic drum 110 is such that the complete line of intelligence information is serially presented at the output circuit of flip-dop FI once for each row of type characters on the printing cylinder, or in other words. a different row of type characters is presented for printing during each successive line time interval. For example. if it is assumed that printing cylinder 132 includes m rows of type characters uniformly spaced about the printing cylinder periphery, and that the complete line of intelligence information is scanned once per revolution of magnetic drum 110, the magnetic drum is rotated through m revolutions for each revolution of the printing cylinder. If, on the other hand, m rows of type characters are disposed about only a portion of the printing cylinder Logical control network 106 is provided to compare the electrical information signals with electrical signals corresponding to the type character which is in a printing position relative to the printing transducers. The logical control network includes a character counter 134 which presents an electrical character signal corresponding to the type character in printing position, and a comparator network 136 which is connected to clock pulse generator 112. hip-flop FI, and character counter 134 for producing and applying to distributor network 108 an electrical output signal each time an information character in the line of intelligence information corresponds to the type character in printing position.

Character counter 134 is connected to clock pulse generator 112 and to fiip-op F0 in order to change the count in the character counter during the last digit time interval of each line time interval to correspond to the next succeeding type character which may be printed. ln addition, the character counter is connected to the output circuit of a flip-op FR which is set to the conduction state corresponding to the binary value one during the last line time interval of each line printing interval in order to reset the count in the character counter to zero after each line of intelligence information has been printed on the printing medium. Flip-flop FR may be actuated from drive mechanism 111, as shown in Fig. 1, or may be actuated from a line time interval counting circuit in the data storage unit if desired.

The function of distributor network 108 is to selectively actuate the printing transducers, in response to output signals from the comparator network, to print each information character in the line of intelligence information as a corresponding type character in its proper line spacing on printing medium 100. The distributor network includes a column counter 138 which is connected to the output circuit of flip-flop FW and to clock pulse source 112 in order to count the number of word time intervals in each line time interval. Thus, the electrical output signal from column counter 138 corresponds to the spacing in the line of intelligence information of the character being compared in cornparator network 136. In addition, the column counter is connected to the output circuit of flip-flop F0 for resetting the counter to zero count during the last digit time interval of each line time interval.

The distributor network also includes a transducer energizing network 140 which is connected to each of the printing transducers and to the output circuits of column counter 138 and comparator network 136. The transducer energizing network is operable under the control of column counter 138 for sequentially rendering the printing transducers energizable and is responsive to an output signal from the comparator network for energizing the particular printing transducer which correspends to the line spacing of the information character being compared.

The high-speed printing system of this invention also includes an order control network 142 which is connected to dip-flops Fx and FW and to clock pulse generator 112, and which is responsive to predetermined binary-coded electrical signals in the line of intelligence information for controlling certain operational sequences of the printing system. For example, the order control network may be utilized to actuate the printing system to skip or Slough a predetermined number of lines on the printing medium between successive printings of two lines of intelligence information. Again, the order control network may be utilized for indicating when additional intelligence information should be entered on magnetic drum 110.

In addition to instituting these operations, the order control network may be employed to temporarily suppress or prevent the printing ef characters on the printing medium while other operations are being performed. As shown in Fig. 1, therefore, the order control network is connected to comparator network 136 by a conductor 144 and to drive mechanism 111 in printer 104 by a conductor 146 in order to provide on-ofi control of the printing operation and to provide for sloughing of printing medium 100. In operation, the control network presents a relatively high-level voltage on conductor 144 when it senses that printing operations should be performed, and a relatively low-level voltage at all other times.

In order to more clearly describe the operation of the high-speed printing system of the present invention, it will be assumed that the printing system is capable of printing 60 different characters corresponding, respectively, to 60 of the 64 possible code combinations of the six-digit binary code. 1t will also be assumed that two of the remaining four combinations of digits correspond to order control signals which are recognizable by order control network 142 for separating the printing operation from the other operational functions of the printing system, and that one of the remaining two binary numbers corresponds to a blank space. The following illustrative table correlates the six-digit binary code with the order control signals and the 60 different type characters which may be printed:

Table I Binary Type Binary Type Binary Type character Number character number character number t] L El 1 M 2 N 3 0 4 P & 5 Q 6 R 7 S 8 T 9 U i A (Blank) l B V C W D X E Y z H i .i St cmi tln 0p pr n s;

order follows. K 111110... Resume printlng. 111111...

If it is assumed that character counter 134 counts sequentially in the conventional six-digit binary code, the rows of type characters on printing cylinder 132 are positioned about thc periphery of the printing cylinder in accordance with the sequence of characters set forth in Table I. For example, in a conventional straight line embodiment of printing cylinder 132, each row of type characters on the printing cylinder may comprise 30 identical raised or elevated type characters disposed longitudinally along the surface of the cylinder in a line substantially parallel to the axis of the cylinder. In accordance with the sequence of type characters shown in Table I, each of the 30 identical type characters in a first row on printing cylinder 132 is capable of printing the numeral 0 through an intervening carbon paper or print ribbon onto an advancing paper record medium, whenever the paper is pressed against the type character by a printing transducer. The type characters in succeeding rows of print cylinder 132 can print the numerals and characters l, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, etc., respectively. 1t will be noted that the binary number 011111 is utilized to represent a blank space in the line of intelligence information and does not actually represent a type character. Consequently, the character counter may be constructed to skip this particular count, or, on the other hand, a vacant type row may be provided on the printing cylinder periphery. In addition, it will be noted that the binary number 111101 is utilized for actuating control network 142 to stop the printing operation, whereas the binary number 111110 is employed to signify that printing operations should be resumed.

To further illustrate the arrangement of the type characters upon printing cylinder 132. inthe following Table l-A, the numeralsOthroughQand the alphabetical charactersAthroughDare arranged in rows and columns in the same relative positions in which the corresponding type characters are disposed on the surface of the described embodiment of printing cylinder 132.

TableI-A s88888888sssssssssssssssss AAAAAAAAAAAAAAAAAAAAAAAAAA BBBBBBBBBBBHBBBBBBBBBBBBBB COCCCCCCCCCCCCCCCCCCCCCCCG DDDDDDDDDDDDDDDDDDDDDDDDDD Additional rows of type characters are provided on printing cylinder 132 for the printing of the remaining characters of the alphabet and for the printing of punctuation marks and other indicia as indicated in Table I. An individual printing transducer is associated with each column of type characters on printing cylinder 132. Thusl for the described Sti-column printing cylinder, there are provided 30 printing transducers designated 130-1, 130-2, to 13B-n, respectively, where n is equal to 30.

These printing transducers, as shown in Fig. l, may be arranged in a single row adjacent printing cylinder 132 and parallel to the rows of type characters, each printing transducer being positioned with respect to the type characters in its associated column so that it is operable when appropriately energized by network 140 for hammering the intervening portion of record medium against the printing face of the type character in its associated column which has reached a printing position immediately opposite the printing transducer. The engagement of record medium 100 with the type character which has reached printing position causes the character to be printed upon the record medium. Thus, for example, printing transducer 1.30-1 is selectively operable for printing any one of the 60 type characters contained in the rst column of printing cylinder 132 upon the corresponding first column of record medium 100, while the printing transducer -3 is similarly operable for printing a predetermined character in the third print column of record medium 100. The particular embodiment of the invention which is to be described is adapted for printing a complete line of information during a single revolution of printing cylinder 132.

If it be assumed that a line of intelligence information which is to be printed contains the numeral 0 at the 12th, 29th, and 30th columns, then as that row of print cylinder 132 which comprises 30 identical 0 type characters attains the printing position, transducers 130-12, 13049,

l 1 and 130-30 are energized by network 140 to print the desired character in the named columns. Similarly, as succeeding rows of type characters attain the printing position, the appropriate transducers are energized, so that by the time a complete revolution of print cylinder 132 has been completed, the complete line of intelligence information is printed upon record medium 100.

The described sequence of operations will be claried at a later point in the specification by the informati-on presented in Table II, and by the descriptive material supplied in connection with Table ll.

When the high-speed printing system of Fig. l is placed in operation, character counter 134 and column counter 138 may assume any arbitrary counts, due to circuit transients and allied phenomena, and may not respectively represent the type character in printing position and the proper line spacing of information characters, as desired. As printing cylinder 132 finishes its first revolution, however, the character counter is reset to zero count during the last digit time interval of the last line time interval through the combined signals from Hip-flop FR,

counter, in turn, control transducer energizing network 140 for sequentially rendering each of the printing transducers energizable in accordance with the column count. Consequently, the printing transducer corresponding `to the line spacing of the compared information character is selectively energized to print each time an electrical signal is applied to the transducer energizing network from comparator network 136.

It may be recalled that the complete line of intelligence information is continuously recirculated in data storage unit 162 and is serially applied to the comparator network once during each line time interval. Accordingly, the information signals representing each character in the line of intelligence information are compared with each different count to which the character counter is indexed, thereby enabling the high-speed printing system of this invention to print the complete line of intelligence information during only one revolution of the printing cylinder. The following table inllustrates the sequence in which a typical space line of intelligence information may be printed:

Table l1 Line spacing or columns Lmetobeprmted ACCOUNT #3207 3 CAMS @i $5 0o Line time intervals:

i 0 0 0 2 0 0 0 3 2 0 3 o o 3 2 0 3 5 0 0 3 2 0 7 3 5 0 0 A 3 2 0 7 3 A 5 0 0 A C C 3 2 0 7 3 C A 5 0 0 A C C 3 2 0 7 3 C A M 5 0 0 A C C N 3 2 o 7 3 C A M 5 0 0 A C C o N 3 2 0 7 3 C A M 5 o 0 A C C o N 3 2 o 7 3 C A M s 5 o 0 ACCO NT 3207 3 CAMS 5 00 ACCOUNT 3207 3 CAMS 5 00 ACCOUNT 3207 a CAMS 5 00 ACCOUNT 3207 3 CAMS 35 00 ACCOUNT #3207 3 CAMS $5 00 ACCOUNT #3207 3 CAMS $5 00 ACCOUNT #3207 3 CAMS 35 00 F0 and clock pulse generator 112. Similarly, at the end 45 Printing medium 100 may be advanced continuously of the first line time interval, the column counter is reset by drive mechanism 111 during the line printing operato zero count by the combined effects of the clock pulse tion or may be advanced intermittently when the comsignals and the output signals from flip-flop F0. Conplete line of intelligence information has been printed. sequently, as the printing cylinder and the magnetic drum Each of these techniques is discussed in more detail in continue to rotate thereafter, the binary counts stored in the abovementioned copending application by Hartley. the character counter and in the column counter are ln addition, the printing medium may be more rapidly continuously indexed from data storage unit 102 and advanced a predetermined number of lines when desired printer 104, thereby respectively presenting electrical out- `by the application to drive mechanism 111 of an electriput signals corresponding to the type character in printcal signal from order control network 142. This funcing position and the information character being comtion of the order control network will be described in pared. more detail below with regard to Fig. 6.

Assume now that a line of intelligence information has lt will be recognized, of course, that the high-speed been entered on magnetic track 114 of the magnetic drum printing system shown in Fig. l may employ numerous and that a. high-level voltage is applied to comparator netcomponent circuits well known to the art and is especially work 136 from order control network 142 to indicate that 60 adaptable to the use of various component circuits well the intelligence information is to be printed. The comknown in the eld of electronic high-speed digital complete line of intelligence information is serially applied puting machinery. Several different electronic circuits to comparator network 136 from flip-op FI once during which may be employed. in the `high-speed printing syseach line time interval, the binary digit signals corretem of this invention will now be described. sponding to each information character being compared As set forth above, the electronic circuits utilized in with the binary digit signals corresponding to the type character counter 134 and comparator network 136 are character in printing position. Each time an informapreferably selected to serially compare the information tion character signal correspondings to a type character characters in the line of intelligence information with signal, an electrical output signal is applied to transducer the count stored in the character counter. More particuenergizing network 140. larly, the logical control network preferably untilizes a During the comparison interval, the count in column serially operable comparator network, for comparing the counter 138 is advanced once each word time interval successive binary information character signals with the in accordance with the spacing in the line of intelligence correspondingly weighted character counter signals, least information of the characters being compared. The elecsignificant binary digits first. lf the signals being corntrical signals corresponding to the count in the column pared are identical, the comparator network applies an electrical output signal to distributor network 108 during the last digit time interval of the associated word time interval.

It will `be recognized that if a serial comparator network is to be utilized in logical network 106, character counter 134 should not only be capable of counting in the binary system of numbers during the last digit time interval of each line time interval, but should also be able to operate as a six binary digit circulating register in order to serially apply to the comparator network, during each word time interval, the six successive binary digits of the binary-coded character count. ln addition, the character counter should be capable of being reset to zero count at the end of each revolution of the printing cylinder to insure that the character count corresponds to the typc character in printing position.

Referring now to Fig. 2, there is shown a high-speed electronic character counter 200 for accomplishing the above-mentioned results, counter 200 including six ipops, F1, F2, F3, F4, F5, and F6, respectively, and six respectively associated gating matrices 201, 202, 203, 204, 205, and 206 which intercouple the input circuits of their associated ilip-ops with the output circuits of flip-Hops FO and FR for controlling the operation of the counter. In order to more clearly describe the structure and operation of the character counter shown in Fig. 2 and of the other electrical circuits to be described later, it will be advantageous to first consider brielly the electrical connections of a typical llip-op circuit and to describe how the mechanization and function of specific gating matrices may be expressed in terms of logical or Boolian algebraic equations.

Each llip-llop or bistable multivibrator includes two input terminals, hereinafter termed the jinput and the kinput terminals, respectively, and two output terminals for producing complementary bivalued electrical output signals hereinafter termed Q and Q, respectively. Signals applied separately to the j-input and k-input terminals set the flip-flop to conduction states corresponding to the binary values one and zero, respectively, while signals applied simultaneously to both input terminals trigger or change the conduction state of the flip-flop. The jand k-inputs to any particular flip-Hop will hereinafter be designated by a numerical sub-script corresponding to the numerical designation of the particular flip-flop.

When the dip-flop is in the conduction state corresponding to the binary value one, signals Q and Q have relatively high-and-low level voltages, respectively, whereas signals Q and Q have relatively low-and-high level voltages, respectively, when the conduction state of the flipllop corresponds to the binary value zero. The Q and Q output signals from any particular flip-flop will hereinafter be designated by a numerical subscript corresponding to the numerical designation of the flip-liep which produces the output signals. For example, the complementary output signals from flip-flop Fo will be designated Q and Q0, while the output signals from FR will be designated QR and QR, respectively. A typical ipliop circuit is shown in Fig. 4 of the copending U. S. patent application, Serial No. 322,665, for Arithmetic Units for Binary-Coded Decimal Computers, by Eldred C. Nelson, filed November 26, 1952.

Each of gating matrices 201 through 206 includes one or more logical and and or" gates, such as gates 208 and 210, respectively, which are interconnected and mechanized in accordance with logical equations representing the various functions of the character counter, such as shift, count, and reset. In operation, each and gate produces a high-level output signal corresponding to the binary value one, only when all of the associated input signals are likewise at their high-level values; whereas each or gate produces a high-level output signal when any one or all of the associated input signals are at their high-level values. The above-mentioned copending application by Nelson also includes a detailed description of the structure of logical gating circuits and the manner in which they may be mechanized in accordance with logical equations. It will be understood, of course, that both the logical gating circuits and the flip-flop circuits may include either vacuum tubes or passive element electronic devices, such as semiconductor diodes and transistors.

For purpose of illustration and further clarification, there is shown in Fig. l2 a typical and gate 250, empolying diode rectiiers and adapted for combining three arbitarary input signals Qx, Qy, and QZ to produce an output signal Q.Q.Qz which is at its high level only when all of the input signals are at their high levels. As shown in Fig. l2, within and gate 250, each of the input signals QX, Qy, and QZ is applied to the cathode of a respectively associated diode rectifier, the anodes of these three diodes being connected together at a common terminal 251. Terminal 251 is connected to an output conductor 252 and is also coupled through a resistor 253 to a source of positive voltage, not shown. In operation, if it be assumed that the level of the voltage source is higher than the high level of any of the input signals, then it is clear that if all of the input signals are at their high levels, the voltage at terminal 251 will be maintained at the common high level. However, if any of the input signals should be at its low level, the associated diode will conduct strongly to maintain the voltage at terminal 251 at the low level. It should be clear that additional signals may be combined in the and gate through provision of additional diode rectiliers.

A typical or gate 260 is illustrated in Fig. 13. Or" gate 260 is adapted for combining the arbitrary input signals QZ, Qy, and QZ to produce a corresponding output signal QZ-l-QZ-t-QZ. Within or gate 260, each of the input signals QX, Qy, and QZ is applied to the anode of a respectively associated diode rectifier, the cathodes of the three diodes being connected together at a common terminal 261. Terminal 261 is connected to an output conductor 262 and is also coupled through a resistor 263 to a point at ground potential. In operation, if any of the input signals is at its high level, the associated diode will conduct strongly to thereby maintain terminal 261 at the high voltage level.

Considering iirst the shifting function of the character counter shown in Fig. 2. it may be recalled that in order to operate with a serially operable comparator network, the binary count in the character counter must be circulated through the counter once during each word time Interval. If it is assumed that the output signals from Hip-flop FE are applied to the comparator network and that the least significant binary digit of the stored count is normally stored in this ip-llop, it is clear that the binary number stored in the counter must be circulated from left to right, as viewed in Fig. 2, in order to sequentially present the successively higher weighted binary digit signals at the output terminals of flip-flop F6. The shifting function of counter 200 may, therefore, be expressed by the following logical equations:

15 where the dot represents tbe logical and" function, Cp represents the clock pulse signal, and Q is a signal indicating that it is not the last digit time interval of a line time interval. For example, if it is not the last digit time interval of a line time interval (Q0), and the binary digit one is stored in flip-ilop FB (Q6), the clock pulse signal is applied to the j-input of ilip-op F1 in accordance with Equation 1l to set the flip-flop to the conduction state corresponding to the binary digit value one. lf prior to the application of the clock pulse, flipop F5 was in its conduction state corresponding to the binary digit value zero (Q5), the clock pulse signal is simultaneously applied to the k-input of flip-flop F3 in accordance with Equation l2 to set Hip-flop FB to the conduction state corcsponding to the binary value zero. Thus the six-digit binary number stored in character counter 200 is completely circulated once each six clock pulses, or in other words, once per word time interval, thereby serially presenting at the output circuit of flipop F6 electrical signals corresponding to the sequential binary digits of the stored binary count.

Considering now the counting function of counter 200, it may be recalled that the stored count must be advanced to the next binary count during the last digit time interval of each line time interval (Q0). It is apparent, however, that in the digit time interval preceding the receipt of signal (Q0), or in other words, during the fifth digit time interval of the last word time interval, the least significant binary digit of the character count is stored in flip-flop F5. Accordingly, during the last digit time interval of the line time interval (Q0), the stored count must be changed to correspond to the next succeeding type character in printing position and must simultaneously be shifted one digit in order to store the least significant binary digit of the new count in flipop F8.

For example, if the binary number 011101 is being circulated in the character counter once during each word time interval, the position of the count in flip-Hops F1 through F6 during the penultimate digit time interval of the line time interval is such that the most significant binary digit is stored in flip-flop F6 while the least significant digit is stored in flip-flop F5, thereby giving the appearance that the binary number 111010 is stored in the counter. During the next digit time interval, therefore, the count must be changed to the next succeeding binary number 011110 with the least significant binary digit again stored in flip-flop F8 and the most significant binary digit again stored in flip-flop F1.

The counting function of character counter 2.00 may be expressed by the following logical equations:

where the plus (Jr) represents the logical nonexclusive or function. For example, Equation signifies that a clock pulse signal (Cp) is applied to the k-input terminal t the above logical equations are simplified forms and may be transformed to other equivalent forms by applying logical network theory. A comprehensive treatment of this subject may be found in copending U. S. patent application, Serial No. 327,131, for Binary-Coded Flip- Flop Counters, by Robert Royce Johnson, filed December 20, 1952. It will also be recognized that if the count is always reset to Zero before the counter has achieved its maximum count, the term (Q5.Q2.Q3.Q4.Q5) in Equation 14 may be omitted since this term is only employed for setting flip-flop F6 to zero after the maximum count has been achieved.

The combined gating functions of character counter 200 may be determined by combining Equations l through 12 with Equations 13 through 24 and introducing a reset function for resetting all flip-flops to zero at the end of each revolution of the printing cylinder. The reset function is derived from flip-flops FR and F0 and is expressed by the function kR=Q0-QR which indicates that a reset pulse is applied to the k-input of each of the counter liipliops during the last digit time interval before printing cylinder 132 starts its next revolution. In addition to providing a reset pulse, it is also desirable to inhibit the application of a clock pulse signal to the j-input of any flip-flop during the digit time interval when the counter is being reset to zero in order to prevent a ilip-llop from being triggered to the conduction state corresponding to the binary value one. This may be accomplished by including the or function jR=(Q0-QR) in the i-input functions to all flip-flops, thus signifying that a pulse may not be applied to a j-input when the counter is being reset.

For example, referring for the moment particularly to llip-op F1, combined shifting-counting-reset functions i1 and k1 may be obtained for the j and k inputs, respectively, of Hip-flop F1 by combining the ils (shift) function, the 1'10 (count) function, and the jR (reset) function, to form the i1 function, and by combining the km, kw, and kB, functions to form the k1 function.

The desired function jl may be defined in the following manner:

Then it is clear that:

f1= Q.'0.Cp+Q6.Qo.Cp @OJ-Enel) (25C) Equation 2SC may be simplified by factoring Cp from one of its terms:

f1= Q6E0+Q6QO EO+R .Cp-Cp (25d) In the logical algebra, a term such as A.A is equal to A. Similarly, Cp.Cp=Cp. Therefore:

Equation 25e may be further simplified by factoring out Q6 to obtain:

i1= 0+QotQ o+RtCp (25h Those skilled in the art will readily recognize that Q0+Q0)=l, since the signals Q0 and Q0 are complementary and, therefore, one of these signals must be at its high (l-representing) level, while the other signal is at its low 4(O-representing) level. (Qo-l-Q0) must, therefore, equal (1|0) which is, in turn, equal to l. By substituting 1 for the term (QO-t-QO) in Equation 25)c there is obtained a complete simplified logical Equation 25 for the desired shifting-counting-reset function il:

The desired shifting-counting-reset function k1, which may be defined by the logical Equation k1=k1slk1c+kR, may be similarly derived from the corresponding separate shift, count, and reset functions.

In the same manner, the j and k gating functions for each of the flip-flops of character counter 200 may be similarly derived.

The complete gating functions of character counter 200, including the shifting, counting and reset functions may be expressed by the following simplified logical equations:

(Gating matrix 204) The mechanization of logical Equations through 36 will be understood more readily by considering the structure of gating matrix 206 which is mechanized according lo Equations and 36. ln mcchanizing the j-input function to flip-op F6 the signals (Q5) and (Q0) are lint combined in an and gate 212 to produce an output signal corresponding to the term (Q5.QO). Signal (QSQO) will have a high (l-representing) level only when both signal (Q5) and signal (Q0) are at their high (l) levels. In the symbology of the logical algebra, il' (Q5) is at a high level (Q5=l) and (Q0) is at a high level (Qozl), then Q5.Q0:l.l=l and, therefore, signal (Q5.QO) will then be at a high (l-representing) level. On the other hand, il Ql and Q01-0, then signal (Q5.QO)=(l.0)-0 and will, therefore, be at a low (0) level. Finally, if (25:0 and Q0==O, then QgQOL- 0.020, and is, therefore, at a low (0) level.

From the foregoing it is clear that the level of an output signal produced by the interaction of two-level electrical signals in an and gate can be discovered by rst substituting the appropriate l or 0 values for the co1- responding symbols in the logical expression which represents the and gate, and then applying the ordinary rules of multiplication; namely, that l.l=l, l.0=0, and 0.0=0. It can also be demonstrated in a similar manner that, for an or gate, the level of its output signal is related to the levels of its input signals in accordance with the following rules which closely resemble the ordinary rules of addition; namely, that l-l-Ozl, 0-|-0=0, and l-|-l=l. Even for a very complicated gating function, composed of a plurality of and and or gates, the level of an output signal can be discovered in the same manner by systematic substitution of appropriate l or 0 values for the input signals and reduction to a final l or 0 value in accordance with the foregoing rules. The signals (55), (Q0), and (6R) are combined in an *and" gate 214 to produce an electrical output signal correspending to the term (5-Q0-QR). The output signals from each of and gates 21.. and 214 are then combined in an or" gate 216 to produce a high-level (l-representing) electrical output signal corresponding to the term (QQ-O-l- Q-QOER). the output signal from the or gate being applied to a clock pulse and gate 220 which is connected to the j-input of hip-flop Fa and has an additional input terminal connected to the clock pulse generator for receiving the clock pulse signal (Cp). Each clock pulse and gate is structurally similar to the other and gates and differs only functionally in that it is selectively operable to pass the applied clock pulse signal to its associated flip-flop input circuit, only when all of the voltage-state signals applied to the input terminals of the and gate are at their high-level l-representing) values.

Equation 36 is similarly mechanized by three and" gates 224, 226, and 228 corresponding to the terms (i2-QOL (QSQO), and (QQ-QR). respectively, an Or" gate 230, and a clock pulse and gate 232 having its output terminal connected to the k-input of flip-flop F6. Gate 228 is located outside of gating matrix 206 because the combined signal (QOQR) is also applied to matricesl 201 through 205 for partially mechanizing Equations 26, 28, 30, 32, and 34. It will be recognized by those skilled in logical algebra, of course, that Equations 25 through 36 may be transformed by Boolian algebra to permit modified mechanizations of the equations, and consequently, the mechanization of the gating matrices shown in Fig. 2 is merely illustrative.

ln the foregoing description of the structure of character counter 200, the following pattern of explanation has been followed: First, logical Equations l through l2 were presented and fully explained, these equations being representative of gating structure which could accomplish the desired shifting function of counter 200. Next, logical Equations i3 through 24 were presented which were representative of gating structure for the accomplishment of the counting function of character counter 200, and also for the accomplishment of an additional shift of information within character counter 200 in conjunction with each increase of count in the counter. Next, the reset function QOQR, for the k-inputs to the flip-flops of counter 200, was presented and explained, and an associated reset function Q-O-'V-R, for the inhibition of clock pulse signals to the j-inputs of the dip-Hops of counter Zth during the reset interval, was also presented and described. Then, to obtain the complete combined shifting-counting-and reset functions represented by logical Equations 25 to 36, the separate corresponding shift functions, count functions, and reset functions were combined and simplified in accordance with the laws of the logical algebra.

Equation 25, for example, which is descriptive of thc gating function for the j-input of iiip-op F1 was obtained by combining the right hand terms of Equations l and i3 with the reset function Q O-l-Qz, It should be noted that Equation l is representative of the shift function for the j-input to flip-flop F1, and that Equation 13 is representative of the count function for the j-input of flip-flop F6. It will be understood that each of the other combined gating functions is similarly obtained by combining the corresponding shift, count, and reset functions for the associated flip-flop inputs. Finally, the exact and definite correspondence between the terms of the logical equations and the corresponding gating structures of Fig. 2 was clarified, by way of example, by relating each of the terms of Equations 35 and 36 to the corresponding gates shown in Fig. 2, it being understood that the terms of cach of the other logical equations is similarly mech- 19 anized by exactly corresponding gating structurees shown in Fig. 2.

To those skilled in the art, the foregoing derivation of the combined gating functions 25 through 36, from separate elementary shift, count, and reset functions, is sufficient to establish the validity of these functions and, therefore, the operability of the structure of the corresponding gating matrices 201 to 206 for the accomplishment of the desired combined shifting-counting-reset functions. However, to further illustrate the operations of counter 200, and to more directly relate the controlling or descriptive logical equations to the gating matrices which they represent, it will be helpful to follow the numerical examples provided below. In these examples the functions js and ke are evaluated, first for the reset of counter 200 at the last digit time of a line printing interval, then for the cyclical shift of counter 200 during the immediately succeeding line time interval, and finally for the advance or increase by one of the character count stored in counter 200 during the last digit time of this line time interval.

During this described sequence of operations, each of the counter Hip-flops, F1 through F6, is first set to the state, by the reset operation, to store the binary number 000000 in the counter. Then, during the shift operation, this number 000000 is continuously shifted in cylical fashion around the counter. Finally, during the count operation, flip-flop FB is changed from the 0 state to the l state, thereby increasing the character count by l from the binary number 000000 to the binary number 000001.

During reset, each of the flip-flops F1 through F6 is to be set to the zero state without regard to its former state. It is clear that during reset a clock pulse signal Cp must be applied to the c-input of each of the flip-flops of counter 200, while the clock pulse signal must be prevented from reaching the j-input of each of the flip-flops. Expressed in the logical algebra, the requirement for successful reset is that during reset, each of the gating functions kl through ku must equal LCP, while each of the gating functions 1', through i6 must equal 0.Cp. Accordingly, it will be demonstrated below that during reset (during the last digit time of the line printing interval), k5=l.Cp while j=0.Cp. The method used below for determining the levels of signals k6 and i6 may also be applied to verify the levels of the other signals i1 through i5 and k1 through k5.

It will be remembered that at reset, flip-flop FR and F0 are both in the l state. Therefore, at reset:

From Equations 35 and 36: is: (Qs-Q-o'l-sQo-.M-CP

Reducing, there is obtained:

In final form, at reset:

Considering next the shifting functions of counter 200, during a shift each ip-op is to be set each digit time to the state prevailing in the immediately preceding flip-flop. Thus, if fiip-op F5 is in its l state during a shift, flipiiop F5 will be set to the 1 state, while if F5 had been in its 0 state, flip-flop F6 will, during shift be set to its 0 state. Thus, it is clear that for successful shift of information from Hip-op F5 to flip-flop F6, signal je should equal Q5.Cp while signal k6 should equal Q-gCp.

20 It will be remembered that during shift, flip-flops FR and FO are both in the 0 state.

Therefore, during shift:

Qa=0 QOZ EF1 50:1

From Equations 35 and 36:

je-lfQs-l-l-CD In final form, during shift:

Finally, to complete this detailed illustration of the operation of counter 200, consider the advance of count in the counter, during the last digit time of the line time interval following reset. During reset, the counter iptiops were set to the number 000000. Then, during the succeeding line time interval, this number was cyclically shifted through the flip-flops of counter 200, a full shift cycle being completed every word time (every six-digit times). Finally, during the last digit time of the line time interval, the counter is to be advanced by l, by changing flip-op F6 to its l state, thereby changing the stored number to 000001. Thus, during count, it is clear that for flip-nop F6, je should equal LCP while k6 should equal 0.Cp.

It will be remembered that, during count, hip-flop F0 is in its l state while ip-op FR is in its 0 state.

Therefore, during count:

Qn=0 Qn:1 512:1 50:0

In addition, it will be recalled that during the first line time interval, the number 000000 is being circulated in character counter 200 and, therefore, all ip-ops F1 through F6 are in their 0 states. Thus, it is certain that flip-op F5 is in its 0 state and, therefore, that:

From Equations 35 and 36:

Reducing, there is obtained:

f,=(0+1).cp k6t0+0+icp In final form, there is obtained:

j=1.Cp k6=0.Cp

Thus, it is clear that for this count, flip-hop F5 will be changed to its l state. In like manner it can be demonstrated that the other Hip-flops of counter 200 are maintained in their 0 states, to thereby obtain the required number 000001 at the completion of this count.

The overall operation of counter 200 may be briefly summarized:

In operation, character counter 200 presents at the output terminals of ip-op F6 electrical signals corresponding to the successive binary digits of the stored assunse character count, these signals repeating once each word time interval throughout the line time interval corresponding to the stored count. At the end of each line time interval, the stored count is advanced in accordance with the counting sequence shown in Table I, in order to compare all of the information character signals in the line of intelligence information with the succeeding type character signal. In addition, at the end of the line printing interval, or in other words, during the last digit time interval of the last line time interval, the character count is reset to zero preparatory to printing the succeeding line of intelligence information.

Referring now to Fig. 3, there is shown a serially operable comparator network 300 which may be utilized with the character counter shown in Fig. 2 for performing the function of logical control network 106 in Fig. l. Comparator network 300 includes an equality hip-flop FE and a plurality of logical and and or gates for determining when the character signals received from flipop F1 in the data storage unit correspond to the count signals received from flip-flop F11 in the character counter.

It may be recalled that in a serially operable comparator network the successive binary digits of each information character in the line of intelligence information are sequentially compared with the correspondingly f' weighted binary digits of the character count, the least significant binary digits being compared first. Thus, as shown in Fig. 3, if each of the six binary digits of the information character correspond to the character count, an output signal (G1) is presented at the output terminal of an and gate 302 and applied to the distributor network for energizing a printing transducer.

Flip-Hop FE is set to the binary value one during the last digit time interval of each word time interval (QW) and is utiii;:ed for sequentially comparing the first tive binary digit signals of the information signal with the first tive binary digit signals of the information signal with the first five binary digit signals representing the character count. lf the rst five binary digit signals of an information signal correspond, respectively, to the rst five binary digit signals of the character count signal, flipflop FE remains in the conduction state corresponding to the binary value one and thus presents a high-level output signal (QE). lf, on the other hand, there is a dissimilarity between any one of the first live digit signals of the information character signal and the corresponding character count digit signal, flip-flop FE is triggered to its other conduction state and presents a low-level output signal. The gating matrix utilized for mechanizing the input functions to ilip-op FE includes and gates 303 and 304 "or gate 306, and clock pulse and gates 308, 310. The mechanization of these gates may be expressed by thc following logical equations:

The operation of the gating structure corresponding to logical Equations 37 and 38 may be readily verified,

During the last digit time of a word time interval, Hip-flop FW is in the l state and, therefore:

Therefore, by substitution in Equations 37 and 38, it may be shown that, during said last digit time:

If ip-ops F1 or Fe should fall into unlike states during these tive digit times, then either signal QPQE or signal Q ,.Qs will attain its high level. For example, if fliptiop F1 is in its 1 state when flip-flop F5 is in its 0 state, then Q,.Q'6=1.1=1, while if F1 is in its 0 state when Fe is in its l state, then Q.Q6=l.1=l. Thus, it is clear that whenever the flip-iops F1 and F6 are in unlike states, signal kE will equal l.(l).Cp=l.Cp and, therefore, will reset flip-Hop FE to its 0 state. Thus, flip-flop FE will remain in its l state at the end of the fifth digit time of a word time interval only if the digit signals produced by Hip-flops F1 and F6 have been identical for the said first five digit time intervals.

lt will be recognized, therefore, that if ip-op FE continues to present a high-level output signal FE at the end of the fifth digit time interval of a word time interval, it is only necessary to compare the sixth or last information character digit signal with the sixth character count digit signal in order to determine if the information character corresponds to the type character in printing posi` tion. Accordingly, the gating matrix for generating the comparator network output signal (G1) may be represented by the following logical equation:

where the signal (QP) is a high-level signal received from the order control network indicating that the printing function of the printer is being performed. The factor (QpQ-l-QpQ-a) in Equation 39, represents equality between the sixth or last digit signals.

In order to clearly described the energization of the printing transducers by the distributor network in response to a comparator output signal (G1), it will be assumed that the line of intelligence information includes 30 sequential infomation characters which are to be printed in 30 corresponding line spaces on the printing medium by 30 corresponding printing transducers. It follows, therefore, that the column counter in the distributor network should have a minimum capacity of thirty counts, in Order to be capable of selectively rendering operable all of the printing transducers.

Referring now to Fig. 4, there is shown a tive-stage flip-flop column counter 400 which includes live dip-flops, F10, F11, F111, F13, and F11, respectively, and associated gating matrices for controlling their sequence of operation. Column counter 400 is connected to flip-Hop Fw in the data storage unit and is responsive to the high-level output signal (QW) which occurs during the last digit time interval of each word time interval for advancing the column count in accordance with the spacing in the line of intelligence information of the sequential information characters being compared in the comparator network. The counter is also connected to flip-flop F0 in the data storage unit and is responsive to its high-level output signal (Q0) during the last digit time interval of each line time interval for resetting the column count to zero at the beginning of the succeeding line time interval.

The gating matrices of column counter 400 are mechanized in accordance with the following logical equations in order to control the counting and reset functions of the associated Hip-flops:

lt will be noted that according to Equation 49 the electrical pulse should be applied to the k-input of ipop F14 when either of two conditions are fulfilled, namely; when (Q) is at its high-level voltage indicating reset to zero, or when flip-flops F111, F11, F12, and F13 are in the conduction state corresponding to the binary value one and" it is the last digit time interval of a word time interval (QW.Q10.Q11.Q12.Q13). lt will be recognized by those skilled in the art, however, that this latter term of Equation 49 is unnecessary because dip-flop F14 will be reset to zero by the signal (Q0) when the counter has counted the required number of columns. Thus, the k-input function of ip-tlop F1, may be mechanized in accordance with Equation 50.

It will be recognized from Equations 40 through 50 that certain combinations of electrical signals appear in several of the equations. In practice, signal combinations represented by common terms in several different equations may be factored out to effect a saving in the number of electrical components employed in the mechanization of the equations. For example, as shown in Fig. 5, signals (Q0) and (QW) are combined in an and" gate 402 for controlling the application of the clock pulse signal (Cp) to the j-input of flip-flop F10. It will be noted from Equations 42 through 48 however, that the j-input function of Hip-flops F11, F12, F13, and F14 also includes the factor (QOQW). Accordingly, the j-input function of flip-hop F11 may be mechanized by combining in an and gate 404 the signal Q from dip-flop F10 and the factor (QO.QW) from and gate 402 to produce the desired function (QO.QW.Q10). Similarly, the j-input function of ip-fiop F12, as given by Equation 44, may be mechanized by combining in and and gate 406 the signal (Q11) from ip-op F11 and the output signal from "and gate 404.

The use of this factoring technique in mechanizing logleal equations is limited by the fact that it is usually del sirable to avoid connecting more than four gating circuits in cascade in order to prevent excessive power drains from the driving flip-flops. Thus, in Fig. 4, for example, the signals (Q0) and (QW) are applied to the j-input of tlip-op F12 through cascaded and gates 402, 404, 406, and a clock pulse and gate 408. A single and" gate 410, therefore, is utilized for mechanizing all but the clock pulse term of Equation 46, the output signal from this gate again being applied to a cascaded and gate 412 for mechanizing Equation 48.

Referring now to Fig. 5, there is shown a transducer energizing network 500 which is connected to both output terminals of each dip-Hop in column counter 400 and which is responsive to the application of comparator out put signal (G1) for selectively energizing the printing transducer corresponding to the count stored in the column counter. If it is assumed that the high-speed print ing system of this invention includes 30 printing transducers, transducer network 500 includes 30 respectively associated blocking oscillators, S10-0, S10-1. 51049, the output circuit of each blocking oscillator being connected to its associated printing transducer. while the input circuits of the blocking oscillator are connected to the output terminals of thirty respectively associated clock pulse and gates, S20-0, S20-1, S20-29. The transducer energizing network also includes a plurality of Z-input terminal and gates, such as gate S30, for combining the output signal (G1) from the cornparator network and various combinations of output sig nais from the column counter to control the actuation of and gates 520-0 through S20-29. The electrical clock pulse signal (Cp) is also applied to one input terminal of each of the four-input terminal and gates for triggering the blocking oscillators when the and gates are actuated to pass the clock pulse. The mechanization of the transducer energizing network and the triggering functions for the 30 blocking oscillators may be expressed by the following logical equations:

Triggering Functions For Blocking Oscillator lt will be recognized by those skilled in the art that certain of these equations are generalized in form, For example, one factor in each of Equations 65, 66, 73, 74, and 77 through 80 may be eliminated by virtue of the fact that the column counter will not count to the binary numbers 11110 and lllll when only thirty transducers are controlled by the transducer energizing network.

In operation, each clock pulse and gate is responsive to the application of high-level voltages from the associated Z-input terminal and" gates for passing the applied clock pulse signal to trigger its associated blocking oscillator, thereby energizing its associated printing transducer. It is apparent from Equations 5l through 80 that a comparator output signal (G1) is necessary to energize each printing transducer, the specific printing transducer energized by a comparator output signal corresponding to the count stored in column counter 400, 4

In the foregoing description of typical component circuits which may be utilized with the synchronous highspeed printing system of this invention as shown in Fig. l. it has been assumed for purposes of illustration that all of the 6-digit binary numbers in the line of intelligence information corresponded to information characters which were to be printed. It may be recalled, however, that predetermined order signals may be entered into the printing system for actuating order control network 142 in Fig. l 

